1. Field of the Invention
The present invention relates to a semiconductor memory device having a burst continuous read function, such as a non-volatile semiconductor memory device.
2. Description of the Related Art
Recently, non-volatile semiconductor memory devices such as flash memories and dynamic RAMs have been improved to have a large capacity. In order to read data from such large-capacity semiconductor memory devices at high speed, the memory cell array is divided into several banks. Each bank is provided with a plurality of sense amplifiers so that the capacity of data lines can be reduced. In addition, burst read architecture using internal addresses different from external addresses is applied.
FIG. 26 shows one configuration of a conventional semiconductor memory device. The same number of bus lines 103 as the burst length is arranged common to banks 101 and 102. One end of the bus lines 103 is connected with a plurality of sense amplifiers included in bank output circuits 104 and 105, and the other end thereof is connected with an output switch circuit 106. The output switch circuit 106 has the same number of synchronous latch circuits 106a and switch circuits 106b as the bus lines 103. The synchronous latch circuits 106a individually latch data transmitted to each bus line 103. The data latched by the synchronous latch circuits 106a are successively output from the switch circuit 106b, which operates in accordance with a clock signal.
In the conventional semiconductor memory device, burst continuous read continuously reading data stored in the several banks is carried out. In this case, the synchronous latch circuit 106a is provided in the output switch circuit 106 so that the data of both banks 101 ad 102 can be held. Thus, it is possible to continuously output data situated on the boundary between the banks 101 and 102.
However, the conventional semiconductor memory device requires as many lines as the bus lines 103 for connecting sense amplifiers 104 and 105 with the synchronous latch circuit 106a of the output switch circuit 106. For example, if the burst length is 8 words (one word: 16 bits), that is, 128 bits, 128 lines are required. In addition, there is a tendency for the burst length to become longer in the future; for this reason, the bus line 103 has large area penalty. Therefore, even if the burst length becomes longer, it is desired to provide a semiconductor memory device which can prevent the bus line area from increasing, and can surely make a read operation.
Incidentally, JPN. PAT. APPLN. KOKAI Publication No. 2001-167593 discloses a technique capable of performing continuous read operation (gapless burst read) in a burst read type synchronous mask ROM.